عنوان مقاله Impact of Parameter Variations on Multi-Core Chips

نام نویسنده

يسنا

پست الکترونیکی

این آدرس ایمیل توسط spambots حفاظت می شود. برای دیدن شما نیاز به جاوا اسکریپت دارید

حجم فایل

407 کیلو بایت

دریافت مقاله

دریافت مقاله

کلمات کلیدی مقاله :
پردازنده هاي چند هسته ايي

چکیده مقاله :
erbated by activity-dependent IR drops. These are exacerbated by temperature-dependent leakage-current variations (i.e., varying the Increasing variability during manufacturing and during runtime are I term) or switching activity that causes voltage droops due to cir- projected for future generation microprocessors. This paper intro- cuit inductance and possibly insufficient decoupling capacitances. duces a pre-RTL, architectural modeling methodology that incor- These three variation sources exhibit a number of feedback loops. porates the impact of manufacturing and runtime temperature vari- Process variations affect leakage, which affects both voltage and ations on delay and power for both combinational logic and SRAM temperature. Temperature then affects leakage forming a feedback structures. The model is then used to show that frequency varia- loop between the two parameters [11]. tions among microarchitectural functional units and among cores This paper focuses on WID variations. D2D variations cause are relatively small in a high-performance microprocessor design. each die on a wafer to have different mean values for a particular However, the impact of within-die systematic process variations on parameter. Gate length is the most common parameter to exhibit leakage power will result in major leakage variation across multiple D2D variation, and is typically modeled by assigning a normally cores on a single chip. WID leakage variation can cause core-to- distributed offset to each die. D2D variations can be dealt with by core leakage to differ by as much as 45%.